High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging

Abstract

In this paper, we propose an equivalent circuit model of through wafer via which has height of 90 mum and diameter of 75 mum. The equivalent circuit model composed of RLCG components is developed based on the physical configuration of through wafer via. Then, the parameter values of the equivalent circuit model are fitted to the measured s-parameters up to 20GHz by parameter optimization method. The proposed model shows through wafer via is dominantly characterized by the capacitance of thin oxide around the via and resistive characteristic of lossy silicon substrate. From simulated TDR/TDT and eye-diagram waveforms of the proposed equivalent circuit model, it is found that parasitic effects of the via cause slow rising time of a signal during transmission of the signal to the through wafer via. However, unlike to the most cases, the slow rising time of through wafer via will not degrade signal integrity severely. At last, we show the effect of dimension of through wafer via on performance of signal transmission using 3D full wave simulation