High-fidelity simulation of integrated single-wafer processing tools for evaluation of scheduling algorithms

Abstract

Semiconductor manufacturing equipments are being integrated into complex systems that perform multiple processes in a single contained unit. An integrated single-wafer processing tool, composed of multiple single-wafer processing modules and transfer robots, has complex re-visit routing sequences, and often has critical post-processing residency constraints at the process modules. The simulation of the single-wafer processing tools presented in this paper is to test and validate on-line schedulers, and evaluate the performance of the integrated single-wafer processing tools before they are actually deployed into the fabs. The developed simulator consists of six components which are a graphic user interface, an emulator, an execution system, a manager, an analyzer and a 3D animator. The overall framework is built by using Microsoft Visual C++, and the animator is constructed by using OpenGL. The emulator has the state models of the process and transfer modules, and control functions that execute unit processes of the transfer robots. The manager checks the states of the robots, and sequentially calls these control functions to fulfill transfer commands. The execution system automatically generates contingencies with pre-defined failure lists, and determines whether the rest of the operable wafers should be further processed or discarded. The animator shows real-time 3D animation of the operation of the processing tools. The analyzer provides various performance measures such as throughput rate, cycle time, utility, and ratio of overtime to residency (ROR). Users can test and evaluate various manufacturing scenarios and configurations of the processing tools and recipes.