High fan-in dynamic cmos comparators with low transistor count

Abstract

In this work, we propose several high fan-in dynamic CMOS comparators with low transistor count, high speed and low power. Major features of the proposed comparators are the rearrangement and reordering of transistors in the evaluation block of a dynamic cell. These comparators can be used as equality comparators, mutual comparators and zero/one detectors, which are widely used in built in self test and memory testing. Furthermore, a 64-bit fast dynamic CMOS comparator is implemented using the proposed dynamic comparator. The measured worst delay of the physical chip with pads is 12 ns.