High electric stress and insulation challenges in integrated microelectronic circuits

Abstract

The insulating layer in the transistor has decreased from 100 nm in the early 1970s to only a few nanometers today. This thin insulating layer gives rise to very high electric fields approaching 1000 kV/mm for an operating voltage of 1 V. Degradation of the insulation during ageing takes place due to the high field and may eventually lead to a breakdown. Currently it seems that the reliability of the insulating layer is one of the factors that may limit a further scaling of the transistor technology. Another threat to the thin insulating layer is electrostatic discharges (ESD) caused by human or machine handling. ESD can generate voltage and current pulses far outside the normal operating regime, and cause breakdown of the insulating layer. This article intends to give a brief introduction to the above-mentioned insulation challenges in integrated microelectronic circuits.