High efficient memory fetch architecture for motion compensation of video decoder

Abstract

To improve the performance of the real-time video decoding under the power-constrained environment, an efficient memory fetch architecture for accessing the motion compensation memory is proposed. According to the feature of accessing the motion compensation memory, the architecture adopts the cache mechanism to buffer the reference data and chooses DMA to access external memories. The architecture can be applied for H.264/AVC, MPEG-4, AVS and other video decoding systems. Compared to the conventional memory fetch module, experimental results show that the proposed architecture reduces 12.8%~16.7% video decoding cycles in H.264 decoding. The timing and the area of this design are both satisfied after synthesized.