High Density metal alloy Interconnections Using Novel Wafer Bonding Approach For 3D IC Packaging Applications

Abstract

The solder is the one of the most interconnect joining material in the denser electronic interconnects. To follow the paradigm, shift towards the Moor’s law, an advanced electronic industry motivated towards the vertical integration of multifunctioning dies. Here the solder is used to connect the dies vertically and also at the packaging level, i.e. Die to PCB (printed circuit board) or silicon interposer. The reliability and electromigration issues of solder, when interconnect dimensions become smaller. This makes the way for involvement of new materials at the die interconnections and at the package level. In this work, the direct bonding of metal alloy (Cu-Cr (0.6 to 1.2% of Cr), which is not only resistive to surface oxidation but also a highly conductive material is proposed. A novel bonding approach which helped in achieving good bonding quality at low temperature and pressure, by creating a density variation in thin film of alloy on silicon substrate. By adjusting the deposition parameters while sputtering, we have created density variation in thin film of Cu-Cr alloy on silicon substrate. Then applied higher temperature to a substrate having high density thin film of Cu-Cr and low temperature to low density varied substrate while performing bonding the used high temperature is $190^{\circ}\mathrm{C}$ with gradient of $30^{o}\mathrm{C}$ for other substrate and applied pressure is $\sim$0.5 MPa for 40 min. The density variation was verified in terms of bond shear strength analysis. we observed the bonding interfacial quality using cross sectional - FESEM and bonding interfacial strength by manually breaking by diamond cutter and sharp blade insertion. High bonding interfacial strength of $\sim$70 MPa, is obtained with proposed bonding method is higher than conventional methodology by $\sim$20 MPa. Using these bonding conditions, we achieved the fine pitch bonding of $10 \mu \mathrm{m}$ features, inspected using IR imaging. The proposed novel methods maybe useful for achieving high density 3D interconnects both at chip and package level, immaterial of the surface roughness of the thin films.