Abstract
At high user densities, FDTS/DF /spl tau/=2 can be efficiently implemented as a 3D-110 detector. The simplicity of the detector facilitates parallel implementations that nearly double the data rate. This high speed version is derived from the sample rate version and enhanced to eliminate the need for cascaded analog sample-and-holds. By factoring out a 1+D term, the number of input terms to the detector summing nodes is reduced to two, providing improved speed for a digital circuit.
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