High Capacitance Density in a Ta2O5 Folded Capacitor Chip

Abstract

By folding Ta2O5 dielectric material into layer arrangements, the charge-storage area of a folded capacitor chip could be easily enhanced. Different from the stack and trench capacitors, such folding configuration could offer a simple geometric structure for lithographic patterning to ensure high quality of the step coverage for each layer. In this study, the capacitance density above 30 fF/µm2 could be obtained by depositing three folded Ta2O5 dielectric material layers separated by 15 nm from each other. The breakdown electric field of a folded capacitor was nearly independent of the layer number. However, the leakage current density was enhanced with increasing number of folding layers because more convex folding corners are first to break down, providing conducting paths for leakage current. The annealing temperature should not exceed 600°C because TiN barrier layer failed to prevent the diffusion of aluminum metal into Ta2O5 films above this temperature.