High Bandwidth Off-Chip Memory Access Through Hybrid Switching and Inter-Chip Wireless Links

Abstract

Off-chip memory performance in many core processors has remained unscaled due to limited pin bandwidth, number of memory controllers and interconnect limitations. It is one of the major bottlenecks for achieving high performance in many core processors, especially with increasing bandwidth requirements as more cores are integrated on a single chip. To achieve high bandwidth memory access, we propose an interconnection architecture with (i) off-chip wireless links for main memory access and (ii) hybrid switching with packet and circuit switching in on-chip mesh network. The off-chip wireless links are designed to provide high data and low energy access to off-chip memory. We enhance the intra-chip network by establishing circuit switch links between caches and memory controllers to provide low latency access, while inter-core communication is achieved through packet switching. The performance evaluation of the proposed architectures shows that they improve performance by 31.09% in runtime and 64.76% in memory access latency as compared to baseline, while consuming 56.57% less energy.