Abstract
A hierarchical Monte Carlo methodology for parametric yield estimation of large analog integrated circuits is presented. The methodology exploits the natural functional hierarchy of a circuit and employs a combination of behavioral and regression modeling to replace device-level circuit simulation where possible. Two related techniques for hierarchical yield estimation are demonstrated on a reasonably large BiCMOS circuit combining discrete-time and continuous-time operation. The hierarchical yield estimates agree well with the benchmark of device-level circuit simulation of the complete circuit and are less computationally expensive.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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