Hierarchical timing verification system

Abstract

A hierarchical timing verification system, based on critical path analysis technique, is described. These techniques permit the system to identify the critical paths of the logic designs. The system performs timing analysis on VLSI designs with sequential circuits and feedback loops. The system traces the design both in the forward and backward directions and computes the arrival times and required arrival times at the primary inputs and primary outputs of the design. The results are applicable to hierarchical VLSI design methodologies. This system has been tested using the logic of Sperry's 1100 series mainframe computer system.