Hierarchical Timing Signoff in High Performance ASIC Design

Abstract

HATS and it is application on a 16.77mm x 16.77mm 32nm chip (chip X) will be introduced in this paper. HATS stands for Hierarchical Timing Signoff. It is a new methodology used to perform timing signoff on an ASIC without the need to do full chip timing runs, which tend to have high memory requirements and long run times on large, complex ASICs. 80% memory and 70% run time are saved in chip X with HATS, with good STA quality.