Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications

Abstract

Nowadays, driven by the consumer demands, the multimedia market is booming and the video coding standards evolve rapidly. A dynamically coarse grain reconfigurable architecture REMUS-II (REconfigurable MUltimedia System 2) is developed as a multi-standards, high resolution, power efficient, and real-time multimedia decoding processor. The hierarchical pipeline is adopted in the REMUS-II for multimedia applications. This paper details the implementation of pipeline optimization techniques for the algorithm and architecture co-design. In each level, the key factors that influence the pipeline performance are analyzed and optimized, including the computational components, the hierarchical memory interfaces, the synchronization mechanisms, and the balanced task assignments. The experimental results show that, compared to original version, the decoding performance of H.264/AVC is improved 2.93 times by the proposed methods. After optimization, the REMUS-II can decode real-time 1080p streams of multi-standards, including H.264/AVC High Profile, MPEG-2 Main Profile, and AVS Jizhun Profile.