Hierarchical multi-dimensional table lookup for model-compiler-based circuit simulation

Abstract

A systematic method to automatically generate hierarchical multi-dimensional table lookup models for compact device and behavioural models with any number of terminals is presented. The method is based on an abstract syntax tree representation of analytic equations. The expensive parts of the computations represented by the abstract syntax trees are identified and replaced by two-dimensional table lookup models. An error-control-based optimisation algorithm is developed to generate table lookup models with the minimal amount of table data for a given accuracy requirement. The proposed method has been implemented in the model compiler MCAST and the circuit simulator SPICE3. Experimental results show that, compared to non-optimised compilation-based simulation, the simulation using the proposed table lookup optimisation method is about 40 times faster and achieves sufficiently accurate results with an error of less than 1–2%.