Abstract
Folding transformation enables synthesis of digital signal processing algorithms described by iterative data flow graphs (DFGs). For a specified feasible folding set, it returns a synthesized hardware architecture described by a hardware DFG. This brief presents hierarchical folding and hierarchical synthesis of iterative DFGs that contain many identical or similar substructures. Instead of performing folding or synthesis on the entire large DFG, the hierarchical folding transformation performs folding or synthesis only on one substructure and then completes the folding process by appropriately changing the number of delays and switch instances in this folded structure. The advantage lies in significant reduction in execution time. Two different approaches to hierarchical folding presented include hierarchical interleaved folding and hierarchical contiguous folding. Experimental results show that the run time increase of the synthesis process for a 20-cascaded fifth-order wave digital filter can be reduced from 2000% to 30% using hierarchical synthesis instead of conventional synthesis, compared with the run time for synthesis of one section.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
