Abstract
Describes recent progress in the area of in-use fault tolerance for a massively parallel array processor. Specifically, the authors have taken the existing architecture of the Hughes 3D Computer and added fault tolerance capability to it. This has been possible to accomplish in modular, uniform way because of the unique circuit partitioning and implementation of the 3D Computer. The single instruction multiple data stream (SIMD) design of the 3D Computer greatly simplifies the control and reconfiguration process, while the fine-grained parallelism permits a high degree of redundancy with very low overhead. They have adopted a hierarchical strategy that mirrors the structure of the 3D Computer itself. Static reconfiguration is supported by special purpose hardware, the Realignment Plane wafer type, which allows them to treat failures uniformly at the row/column, processing element, and functional element levels. >
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