Abstract
Today’s prevailing video systems demand extreme performance that can be efficiently supported by parallel computing engines. This paper presents a novel hierarchical circuit-switched ring network on chip (called HrNoC) for the parallel engines, of which the cost, power, and latency have been extensively optimized from bottom up. First, a communication scheme “wave” is proposed for both intra-ring and inter-ring routing-paths built with rapid stream transactions. Then, a cost-effective bridge featuring deterministic packet traversal and deadlock avoidance is designed for flexible inter-ring connections. Finally, varied configurations of hierarchical rings are exploited by system specification and application mapping. In experiments, the proposed HrNoC on a 16-core multicore system performs about 50% latency reduction, 1/3 area cost, and 1/5 power consumption, compared with a packet-switched mesh NoC.
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