Abstract
AbstractThis paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection v.2 (HIBI) aims at maximum efficiency and energy saving per transmitted bit combined with guaranteed quality-of-service (QoS) in transfers. Other features include support for arbitrary topologies with several clock domains, flexible scalablility in signalling and run-time reconfiguration of network parameters. HIBI has been implemented in VHDL and SystemC and synthesized in 0.18 CMOS technology with area comparable to other NoC wrappers. HIBI data transfers are shown to approach the maximum theoretical performance for protocol efficiency.KeywordsTime SlotIntellectual PropertyClock CycleIntellectual Property CoreClock DomainThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
