HFNet: A CNN Architecture Co-designed for Neuromorphic Hardware With a Crossbar Array of Synapses.

Pengfei Sun,Yansong Chua,Arindam Basu,Roshan Gopalakrishnan,Ashish Jith Sreejith Kumar

doi:10.3389/fnins.2020.00907

Abstract

The hardware-software co-optimization of neural network architectures is a field of research that emerged with the advent of commercial neuromorphic chips, such as the IBM TrueNorth and Intel Loihi. Development of simulation and automated mapping software tools in tandem with the design of neuromorphic hardware, whilst taking into consideration the hardware constraints, will play an increasingly significant role in deployment of system-level applications. This paper illustrates the importance and benefits of co-design of convolutional neural networks (CNN) that are to be mapped onto neuromorphic hardware with a crossbar array of synapses. Toward this end, we first study which convolution techniques are more hardware friendly and propose different mapping techniques for different convolutions. We show that, for a seven-layered CNN, our proposed mapping technique can reduce the number of cores used by 4.9–13.8 times for crossbar sizes ranging from 128 × 256 to 1,024 × 1,024, and this can be compared to the toeplitz method of mapping. We next develop an iterative co-design process for the systematic design of more hardware-friendly CNNs whilst considering hardware constraints, such as core sizes. A python wrapper, developed for the mapping process, is also useful for validating hardware design and studies on traffic volume and energy consumption. Finally, a new neural network dubbed HFNet is proposed using the above co-design process; it achieves a classification accuracy of 71.3% on the IMAGENET dataset (comparable to the VGG-16) but uses 11 times less cores for neuromorphic hardware with core size of 1,024 × 1,024. We also modified the HFNet to fit onto different core sizes and report on the corresponding classification accuracies. Various aspects of the paper are patent pending.

Highlights

Over the past decade, GPUs have emerged as a major hardware resource for deep learning tasks
In 3.2, we propose a hardware-friendly convolutional neural networks (CNN), the HFNet, and report on (1) the cores required for mapping, (2) classification accuracy and cores required with and without maxpooling and full connections, (3) classification accuracy and cores required for different core sizes, (4) comparison of the MobileNet and HFNet, and (5) the results when grouped convolution replaces depthwise separable convolution
We identify deep learning techniques to avoid which result in poor core utilization or even result in core matrix splitting

Summary

Introduction

GPUs have emerged as a major hardware resource for deep learning tasks Fields, such as the internet of things (IoT) and edge computing are constantly in need of more efficient neural-network-specific hardware (Basu et al, 2018; Deng et al, 2018; Alyamkin et al, 2019; Roy et al, 2019). In analog devices, using Kirchoff ’s current law, the total current flowing into each neuron from the respective bit lines is the sum of currents flowing through each intersection in every column This corresponds well with how inputs in a neural network is the weighted sum of input voltages ( (Input × Weight)). In the chip architecture, we have a limited number of neuromorphic cores and a limitation in the core size of each neuromorphic core and the fan-in/fanout degree of each neuron (Ji et al, 2018; Gopalakrishnan et al, 2019b)

Methods

Results

Conclusion