Hf₀.₅Zr₀.₅O₂ Ferroelectric Embedded Dual-Gate MoS₂ Field Effect Transistors for Memory Merged Logic Applications

Abstract

In this letter, a combination of multi-gate field effect transistor with ferroelectric is proposed for a new concept of memory merged logic device. For the first time, dual-gate MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> field effect transistor (FET) with a Hf <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Zr <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) back gate insulator is fabricated. Because of the manipulation of charge density in the channel by both electric field from the top/back gates and the polarization field form the HZO, the ferroelectric embedded dual-gate (FEDG) MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FET can work as a normal n-type top-gate MOSFET or a ferroelectric memory with 1 V memory window and retention time up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> s, separately or simultaneously. In memory merged logic operation, the output current of the devices depends on the top-gate voltage, back-gate voltage and the polarization of the HZO, which greatly extend the possible function that one transistor can implement. The FEDG FET has the benefits of diminishing the power dissipation of inter connection between logic and memory arrays in the integrated circuit, and reducing the number of transistors in circuits comparing to standard MOSFET configurations, which shows a great potential in the ultra-low power consumption in memory computing (IMC) and neuromorphic computing (NC) applications.