Hexagonal TSV Bundle Topology for 3-D ICs

Abstract

Through-substrate vias (TSVs) are key for enabling 3-D integrated circuits (ICs). A hexagonal topology for TSV bundles in 3-D ICs is introduced in this brief. The topology exhibits superior symmetry as compared to the standard mesh topology. A comparison between the hexagonal and mesh topologies in terms of area per TSV, capacitive coupling, effective inductance, and shielding characteristics is offered. The hexagonal topology exhibits a reduction of 13% and 7% in, respectively, area per TSV and capacitive coupling. In addition, a two- to three-orders-of-magnitude decrease in effective inductance within the hexagonal topology is observed.