Abstract

The information, and communication technologies (ICTs) are increasingly merging with the conventional power systems. For the design, and development of modern AC/DC grids with integrated renewable energy sources, the system-level control schemes with ICTs involved should be evaluated in a co-simulation framework. In this work, a heterogeneous hardware real-time co-emulator composed of FPGAs, many-core GPU, and multi-core CPU devices is proposed to study the communication-enabled global control schemes of hybrid AC/DC networks. The electromagnetic transient (EMT) power system emulation is conducted on the Xilinx FPGA boards to provide nearly continuous instantaneous waveforms for cyber layer sampling; the communication layer is simulated on the ARM CPU cores of the embedded NVIDIA Jetson platform for flexible computing, and programming;, and the control functions for modular multi-level converters are executed on GPU cores of the Jetson platform for parallel calculation. The data exchange between FPGAs, and Jetson is achieved via the PCI express interface, which simulates the sampling operation of the AC phasor measurement unit (PMU), and DC merging unit (DC-MU). The power overflow, and DC fault cases are investigated to demonstrate the validity, and effectiveness of the proposed co-emulation hardware architecture, and global control schemes.

Highlights

  • WITH the development of modern power systems, the information and communication technologies (ICT) are increasingly involved in the control, protection and normal operation of power system equipment and infrastructure, which introduced the so called cyber-physical system concept

  • The existing solutions are not applicable to the proposed co-emulation architecture, because: 1) using the created virtual network, new interfaces are required to be developed for synchronizing the measurement data, which is time-costly and make the real-time co-emulation infeasible; 2) for large-scale AC/DC test power systems, hundreds of nodes need to be instantiated if each node is regarded with a phasor measurement unit (PMU) installed, each node needs to receive the corresponding sampling data and generate data packets, which greatly increases the simulation latency

  • After the PMU measurement on the Bus38 and Bus36 are collected by PDC2 and sent to the system-level controller located on DC Bus Bb-A1, the corresponding control commands that instruct the wind farms to decrease the generation are sent to the two wind farms; and the commands that change the reference values of power flows are sent to the converter Cb-C2 and Cb-D1

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Summary

INTRODUCTION

WITH the development of modern power systems, the information and communication technologies (ICT) are increasingly involved in the control, protection and normal operation of power system equipment and infrastructure, which introduced the so called cyber-physical system concept. BRAM-1 via the PCIe driver function at a configurable rate; for the control command delivery, the corresponding instructions can be written to BRAM-2 at any time to change the circuit parameters in the FPGA computation These operations do not influence the normal simulation in the power system domain, which makes the real-time EMT emulation possible. The existing solutions are not applicable to the proposed co-emulation architecture, because: 1) using the created virtual network, new interfaces are required to be developed for synchronizing the measurement data, which is time-costly and make the real-time co-emulation infeasible; 2) for large-scale AC/DC test power systems, hundreds of nodes need to be instantiated if each node is regarded with a PMU installed, each node needs to receive the corresponding sampling data and generate data packets, which greatly increases the simulation latency. The measurement data packet generation function is included in the architecture, which is used to simulate the behaviour of PMUs and DC-MUs that sample measurement data from power system and encapsulate the measurement into network packets to be sent to the PDC

HARDWARE IMPLEMENTATION OF TEST SYSTEM
CASE STUDY 1
CASE STUDY 2
CONCLUSION
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