Abstract
Monolithic integration of III-V semiconductor devices on Silicon (Si) has long been of great interest in photonic integrated circuits (PICs), as well as traditional integrated circuits (ICs), since it provides enormous potential benefits, including versatile functionality, low-cost, large-area production, and dense integration. However, the material dissimilarity between III-V and Si, such as lattice constant, coefficient of thermal expansion, and polarity, introduces a high density of various defects during the growth of III-V on Si. In order to tackle these issues, a variety of growth techniques have been developed so far, leading to the demonstration of high-quality III-V materials and optoelectronic devices monolithically grown on various Si-based platform. In this paper, the recent advances in the heteroepitaxial growth of III-V on Si substrates, particularly GaAs and InP, are discussed. After introducing the fundamental and technical challenges for III-V-on-Si heteroepitaxy, we discuss recent approaches for resolving growth issues and future direction towards monolithic integration of III-V on Si platform.
Highlights
Silicon (Si) has long been of great importance in a wide range of micro/nanoelectronics industry because it offers numerous benefits, such as large wafer size, low cost, abundant source, and mature manufacturing technology [1]
To obtain GoVS template, n-type on-axis (001) Si substrates patterned with SiO2 stripe were chemically etched by potassium hydroxide (KOH) solution to form trench structure exposing (111) facets, and subsequently the GaAs nanowires were selectively grown on the V-grooved Si by metal-organic chemical vapor deposition (MOCVD)
To obtain GoVS template, ntype on-axis (001) Si substrates patterned with SiO2 stripe were chemically etched by potassium hydroxide (KOH) solution to form trench structure exposing (111) facets, and subsequently the GaAs nanowires were selectively grown on the V-grooved Si by metal-organic chemical vapor deposition (MOCVD)
Summary
Silicon (Si) has long been of great importance in a wide range of micro/nanoelectronics industry because it offers numerous benefits, such as large wafer size, low cost, abundant source, and mature manufacturing technology [1]. Notwithstanding the tremendous efforts on III-V-on-Si heteroepitaxy, the monolithic integration of III-V devices on Si-based PICs or ICs is not deployed yet, mainly due to the material dissimilarities between III-V and Si introducing a high density of defects, such as antiphase boundaries (APBs) and threading dislocations (TDs) [24,26]. It is crucial to achieve monolithic integration of III-V/Si which enables cost-effective and dense integration In this regard, growing high-quality III-V semiconductors on Si is a key pathway towards monolithic integration of III-V devices on Si-based PICs or ICs. For high-quality III-V layer on Si, the main challenges, namely the high density of various defects caused by material dissimilarities, such as large lattice mismatch, polar-on-nonpolar growth, and different coefficient of thermal expansion, should be tackled [12]. We summarize the current status and discuss the potential future of III-V-on-Si heteroepitaxy
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