Abstract
The CMS Level-1 Trigger at HL-LHC and associated upstream systems employ more than 10000 25 Gb/s optical links, transferring almost a Pb/s of data synchronously between the different back-end processing nodes. Stable operation of these links is essential to avoid the injection of erroneous signals into the trigger path, potentially leading to a flood of false triggers or data loss. The Hermes protocol, implemented on Xilinx UltraScale+ FPGAs, provides this stability while operating at asynchronous, industry standard line rates. The protocol design as well as results on the performance from extensive testing are presented here.
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