Heavy metal contamination during integrated-circuit processing: Measurements of contamination level and internal gettering efficiency by surface photovoltage

Abstract

Crystallographic defects present in device active areas form localized dark current generation sites. The current generation rate is a function of decoration of these defects by heavy metals. These defects cause yield degradation of the integrated circuits. The surface photovoltage (SPV) method, which measures minority-carrier diffusion lengths, has been applied successfully to monitoring in real time the heavy metal contamination level in processing lines, and to identifying sources of heavy metals. Heavy metal contamination has been monitored on the control floating zone (FZ) wafers, which were exposed to certain critical processing steps. A threshold contamination level exists beyond which the probability of crystallographic defect decoration and the formation of stacking faults increases dramatically. This level is different for the different defects, processes and different types of silicon wafers (i.e. those obtained by FZ, magnetic Czochralski (MCZ), internal gettering (IG), Czochralski and epitaxy methods). Surface photovoltage was also used to measure non-destructively, in real time, the denuded zone depth in IG wafers. In IG wafers, values of diffusion length are proportional to the denuded zone depth. Bulk oxygen precipitate densities were also measured by SPV. Prior to these measurements the denuded zone was removed from the back of the wafer by etching. Good correlation between the yield reduction charge-coupled device imagers, complementary metal-oxide-semiconductors, dynamic random access memories and bipolar devices and increases in the contamination level as measured by SPV has been reported in literature. Also, good correlation between the yield of these circuits and the efficiency of IG, as measured by SPV in IG wafers after completion of the fabrication sequence, was established. These issues will be discussed in this paper.