Heavy ion test results of RHBD standard cells and memory in a 110nm bulk CMOS process

Abstract

This paper describes heavy ion testing and results gathered from a test chip produced in the ON Semiconductor 110nm process. Content on this test chip includes conventional CMOS standard cells augmented with Radiation Hardened By Design (RHBD) library elements and dual port SRAM with error correction code (ECC) developed specifically for SEE concerns and high performance operation. Favorable test results are presented showing SEE performance of the Self Restoring Logic (SRL) cell to 140 MeVcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg onset LET for upsets. Additionally, SRL based polynomial counters performed flawlessly at 700MHz to an LET of 78 MeVcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. SEL protection of the bulk CMOS process using the special support cells is described. SRL flip flop results are compared to legacy DICE and SERT flip flop architecture results.