Heating Effects in Nanoscale Devices

Abstract

The ever increasing demand for faster microprocessors and the continuous trend to pack more transistors on a single chip has resulted in an unprecedented level of power dissipation, and therefore higher temperatures at the chip level. Thermal phenomena are not directly responsible for the electrical functionality and performance of semiconductor devices, but adversely affect their reliability. Four major thermally-induced reliability concerns for transistors are: (1) degradation of device thermal characteristics due to heating effects, (2) failure due to the electrostatic discharge phenomenon, (3) stresses due to different rates of thermal expansion of transistor constituents, and (4) failure of metallic interconnects due to diffusion or flow of atoms along a metal interconnect in the presence of a bias current, known as the electromigration phenomenon. Self-heating of the device and interconnects reduces electron mobility and results in a poor or, at best, non-optimal, performance of these devices and structures. Fig. 1 shows the trend of the average power density for high-performance microprocessors according to the ITRS. No flattening or slower decelerated increase will occur after the introduction of the Silicon on Insulator (SOI) technology. It should be noted that the power density shown in Fig. 1 is the average power density, i.e. the total chip power divided by the chip area. In logic circuits, such as microprocessors, the power is non-uniformly distributed. There are portions of the chip of quite low power dissipation (memory blocks) and, on the other hand, portions running at full speed with high activity factors where the power density can easily be more than a magnitude higher than the average chip power density from Fig. 1. The latter portions will create hot spots with quite high local temperature. The power density in the active transistor region (essentially the channel region underneath the gate) is again much higher than the average power density in a hot spot when the transistor is in the on-state. Thus, the treatment of self-heating and the realistic estimation of the power density is quite a complex problem. Sometime within the next five years, traditional CMOS technology is expected to reach limits of scaling. As channel lengths shrink below 22 nm, complex channel profiles are required to achieve desired threshold voltages and to alleviate the short-channel effects. To fabricate devices beyond current scaling limits, Integrated Circuits (IC) companies are simultaneously pushing planar, bulk silicon CMOS design while exploring alternative gate stack materials (high-k dielectrics and metal gates), band engineering methods (using 3