Heat Conduction in Printed Circuit Boards: Part I — Overview and the Case of a JEDEC Test Board

Abstract

Addressed in the present study is the required accuracy in assuming equivalent thermal conductivities of printed circuit boards (PCBs) in the thermal analysis of electronic equipment. The required accuracy depends on the morphology of PCB and the thermal boundary condition. Out of various PCB morphologies two are considered as representatives in the extreme ends of PCB size and thermal conditions; one is a JEDEC test board having a large convection-cooled area, and the other is a small board in contact with a large solid thermal mass. The major focus of the present paper is on the case of a JEDEC test board measuring 11 cm × 11 cm and carrying a ball grid array package (4 cm square). Geometric complexity in the through-via zone under the package needs to be reduced by suitable modeling in order to simplify the analysis. In exploring modeling strategies the analyses were performed on three models. Level-one model includes the details of through-vias, and the computation is resource intensive. Level-two model is composed of two orthotropic media having pairs of different equivalent thermal conductivities, one corresponding to the via zone and the other to the rest. Level-three model is a thermal resistance network model derived from numerical/analytical composite analysis. Comparison of the results on the three models proves that the accuracy of temperature prediction is in general insensitive to the equivalent thermal conductivity values due to the dominant role of surface heat transfer on the temperature level of PCB.