應用於HDTV1080p之H.264/AVC立體高級規範立體影像幀間預測演算法研究及其電路架構設計與實現

Abstract

Three-dimensional (3D) video offers a high-quality and immersive multimedia to human eyes via sender transmission. In 3D video systems, stereo video coding plays an important role because stereo video doubles the amount of data, comparing with the tradition 2D video. Therefore, stereo video coding must solve this problem so it can effectively reduce the original large amount of date, whereas maintain the good quality in stereo video. For this reason, this thesis stereo video coding will be divided into two stages. At the first stage, we propose fast inter coding algorithm applied in H.264/AVC stereo video coding system; and at the second stage, we propose fast inter coding architecture applied in H.264/AVC stereo video coding. In terms of algorithm, we propose a fast motion/disparity estimation algorithm based on the coarse-to-fine technique. The proposed algorithm is applied to integer motion/disparity estimator of the H.264 stereo encoder. It performs the local full search on pixels around the selected candidates to obtain the 41 MVs or DVs. The proposed algorithm that compared with full search block match algorithm can keep the good quality and save the amount of computation algorithm. Moreover, we propose an early disparity termination algorithm base on model-based scheme. The threshold values are determined by some equations. When motion estimation is finished, we compare the SAD value of some points with threshold values. If SAD value is smaller than threshold value, disparity will be terminated. This algorithm can also increase with the quality and reduce the computation amount. In the Hardware, combining the proposed coarse-to-fine algorithm and module-based early disparity termination algorithm, we propose fast inter coding architecture applied in H.264/AVC stereo video coding. This architecture also allows us to use the same computation unit to estimate left view motion and right view motion/disparity. We also use memory preload technology to save stereo video coding time. The implementation result shows that the proposed Stereo inter prediction processor has 130K logic gates with core size 2.8 × 2.8 mm2. Moreover, In the TSMC 0.09mm 1P9M CMOS process, the H.264/AVC Stereo High Profile HDTV1080p applications at 250 MHz.