HDL based simulation framework for a DPA secured embedded system

Abstract

Side Channel Analysis (SCA) are still harmful threats against security of embedded systems. Due to the fact that every kind of SCA attack or countermeasure against it needs to be implemented before evaluation, a huge amount of time and cost of this process is paid for providing high resolution measurement tools, calibrating them and also implementation of proposed design on ASIC or target platform. In this paper, we have introduced a novel simulation platform for evaluation of power based SCA attacks and countermeasures. We have used Synopsys power analysis tools in order to simulate a processor and implement a successful Differential Power Analysis (DPA) attack on it. Then we focused on the simulation of a common countermeasure against DPA attacks called Random Delay Insertion (RDI). We simulated a resistant processor that uses this policy. In the next step we showed how the proposed framework can help to extract power characteristics of the simulated processor and implement power analysis based reverse engineering on it. We used this approach in order to detect DPA related assembly instructions being executed on the processor and performed a DPA attack on the RDI secured processor. Experiments were carried out on a Pico-blaze simulated processor.