HCl + GeH4 etching for the low temperature cyclic deposition/etch of Si, Si:P, tensile-Si:P and SiGe(:B)

Abstract

We have investigated a few years ago the cyclic deposition/etch of Si(:P) in the Sources/Drains regions of MOS transistors. Blanket growth occurred at 550 °C while materials on dielectrics were selectively etched at 600 °C with GeH4-catalyzed HCl. Thanks to the presence of Ge atoms close to the surface, Si etching was indeed much faster with HCl+GeH4 than with HCl. Performing those etches at 550 °C instead of 600 °C would be advantageous, as the thermal budget would be lower (3D integration), the throughput higher and amorphous Si(:P) etching easier. We have therefore quantified the impact of temperature, pressure and flows on the HCl+GeH4 etch rate of monocrystalline Si, (doped or tensile) Si:P ([P] = 1020 or 1.5 × 1021 cm−3) and Si0.7Ge0.3(:B) ([B] ∼2 × 1020 cm−3) for channel and raised sources and drains applications. Increasing the etch pressure and reducing the H2 flow resulted in linear increases of the Si Etch Rate (ER). Decreasing at 650 °C the HCl flow yielded (i) definitely higher Si ER at 20 Torr and (ii) explosively higher Si ER at 90 Torr. We have then quantified, with those reduced flows, the impact of temperature on etch rate. 90 Torr etch rates were always higher than those at 20 Torr. We had at 20 Torr exponential etch rate decreases as the temperature decreased, with SiGe:B ER higher than SiGe ER, which were much higher than Si ER. The former was due to surfaces richer in Ge (and B) atoms, which acted as catalysts for H and/or Cl desorption. We otherwise had Si:P ER which were higher than Si ER, which were themselves higher than t-Si:P ER. Going over to 90 Torr yielded reasonable SiGe(:B) (Si, Si:P and t-Si:P) ER at temperatures as low as 500 °C (550 °C).