Abstract
This paper addresses both the detection and elimination of hazards in different configurations of CMOS circuits. The analysis of hazards in combinational circuits using logic gates and their hazard-free designs have already been treated in detail in many standard text books. However, the current trend in the design of switching circuits have shifted from the mere interconnection of logic gates to more complex networks of MOS transistors. This necessitates the analysis of hazards in CMOS and pass networks, and their elimination in these networks. This paper gives the necessary and sufficient conditions for the presence of hazards in CMOS networks. The presence of hazards have been verified using SPICE simulation. Different methods of eliminating hazards in these networks are presented. In addition, new design techniques for the hazard-free design of optimal CVSL circuits are also given in this paper.
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