Abstract
In the viewpoint of reliability implication and cost effectiveness of three phase inverter, there should be less device count in inverter topology and fewer losses in the semiconductor switches. The earlier reported less device count topology by many research groups are facing the problem of Total Harmonic Distortion (THD). The imperfect design value of DC link capacitor is the main reason of Harmonic Distortion (THD) problem. The ripple in the dc link voltages of Voltage Source Inverter (VSI) is leads to additional harmonics distortion. This paper present the simulative view of minimization of the harmonic reduction in proposed topology using improved DC link capacitor. The said approach is verified using PSIM (Power Simulator) software.
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