Abstract
This chapter describes a new system-level algorithm for hardware/software (HW/SW) cosynthesis of multirate real-time systems on heterogeneous muitiprocessors. The algorithm synthesizes the hardware, software, and memory hierarchy based on multiprocessor target architecture to meet the performance constraints with minimal cost. Memory hierarchies (caches) are essential for modern embedded cores to obtain high performance. They also represent a significant portion of the cost, size, and power consumption of many embedded systems. The algorithm synthesizes a set of real-time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. Unlike previous work in cosynthesis, the algorithm not only synthesizes the hardware and software portions of the applications, but also the memory hierarchies. It chooses cache sizes and allocates tasks to caches as part of cosynthesis. The algorithm is built on a task-level performance model for memory hierarchies.
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