Abstract

syntax trees serve a common role as a standard representation of software code during compilation. In order to develop a common AST representation for multiple software languages such as Ada, JOVIAL, and C++, the Arcadia group developed IRIS. By using IRIS as a common foundation, a number of software engineering projects have been able to exploit a common front end and support multiple languages. One Air Force Research Lab software maintenance project exploits this approach to port older JOVIAL code into Ada 95 [2]. This paper addresses efforts to provide an interface between VHDL models and Ada software via a common abstract syntax tree by exploiting AIRE and IRIS. We discuss this interface, language construct limitations, and the potential for solidifying the hardware/software interface. A number of very interesting applications exist for such an interface between VHDL hardware models and software written in languages such as Ada. Models in hardware can be ported to software for implementation, and vice-versa. In addition, some of the Arcadia software engineering tools built upon IRIS provide analysis capabilities that could prove quite useful for VHDL. The potential for greatly improving the state of the art in hardware modeling via these tools is discussed. By exploiting state of the art software engineering tools and formats, a bridge between hardware models and software code can be constructed. This bridge has great potential for enhancing the systems design effort by supporting relatively effortless migration between the hardware and software domains in addition to enabling an integrated analysis tool suite. In response to a perceived need for additional support of abstract system design and specification, a system-level design language development effort sponsored by the Industry Council continues to investigate needs in this area in preparation for extensions to VHDL or the possible development a new system description language [3]. Significant related research is in progress which could be exploited in developing the system level design language. There is a wealth of work going on with VHDL and hardware design, synthesis, and test. The same can be said of work for software engineering with Ada and with process improvements. Complex systems include both hardware and software components. Significant recent attention focuses on how to specify, design, and verify the hardware and software together. Current standardization efforts related to codesign focus on co-simulation approaches in the short term [4] and general codesign/systems design support in the long term. The goal of this effort is to bring together research results from both communities to improve systems design capabilities. Long-term software engineering experience proves Ada to be effective for cost-effectively managing large program development and maintenance efforts, particularly when compared to languages such as C [5,6]. Ada is syntactically similar to VHDL, which makes it attractive as a basis for the software domain. Despite the end of the DoD Ada mandate, Ada remains a powerful language often chosen for weapons systems development [7]. Ada provides strong typing, encapsulation via the package mechanism, and supports generics among other features. Ada 95’s object oriented programming, real time, and programming in the large features makes Ada highly competitive. Yet, opposition to Ada has hindered general adoption by industry. VHDL enjoys significant use in the design automation industry.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.