Hardware-in-the-loop Simulations of Inverter Faults in an Electric Drive System

Abstract

Power Hardware-in-the-loop (PHIL) and Controller-HIL (CHIL) simulations have several benefits with respect to electric drive system testing. Since there is a reduced chance of equipment damage with CHIL and PHIL simulations, they are particularly suited to study the impact of inverter faults. This paper presents PHIL simulations to emulate machine behavior in the event of such inverter faults. The faults considered here are the gate unit failure (or the device open circuit fault) of one or more switches in the driving inverter. The process of voltage sensing, especially during faults, is first explained in this paper. It is shown that the driving inverter terminal voltage is defined, even during faults, thus allowing the possibility to control the PHIL system during these conditions. Experimental results are presented for the same fault conditions from the PHIL system and a prototype permanent magnet synchronous machine (PMSM) coupled to a dc dynamometer. A close match between the two results is shown, proving the ability to operate the PHIL system in current control mode even during such faults. A close match between the two results also proves the sufficiency and utility of PHIL simulations to study driving inverter faults.