Abstract
This paper presents hardware-efficient Delta Sigma linear processing circuits for the next generation low-power VLSI devices in the Internet-of-things (IoT).We first propose the P-N (positive-negative) pair method to manipulate both the analog value and length of a first-order Delta Sigma bit sequence. We then present a binary counter method. Based on these methods, we develop Delta Sigma domain on-the-fly digital signal-processing circuits: the Delta Sigma sum adder, average adder and coefficient multiplier. The counter-based average adder can work with both first-order and higher-order Delta Sigma modulators and can also be used as a coefficient multiplier. The functionalities of the proposed circuits are verified by MATLAB simulation and FPGA implementation. We also compare the area and power between the proposed Delta Sigma adders and a conventional multi-bit adder by synthesizing both circuits in the IBM 0.18-μm technology. Synthesis results show that the proposed Delta Sigma processing circuits can extensively reduce circuit area and power. With 100 inputs, a Delta Sigma average adder saves 94% of the silicon area and 96% of the power compared to a multi-bit binary adder. The proposed circuits have the potential to be widely used in future IoT circuits.
Highlights
The Internet-of-Things (IoT) demands ubiquitous devices that collect and process sensed data and transmit back to the central node through various network interfaces [1]
The Delta Sigma bit-streams are fed into the proposed Delta Sigma processing circuits, which include the sum adder and the average adder
The processing circuits are coded in Verilog and simulated by the Xilinx ISE isim simulator and implemented on an Opal Kelly Spartan-3 field programmable gate array (FPGA) board [36]
Summary
The Internet-of-Things (IoT) demands ubiquitous devices that collect and process sensed data and transmit back to the central node through various network interfaces [1]. Biomedical sensors in the IoT targets an important application of the “unmanned medical nursing system” [1], which could alleviate increasing medical costs as the baby boomers enter retirement [4] Such wearable and implantable biomedical sensors demand low-complexity, low-power, high-resolution and high-reliability digital signal processing (DSP) circuits, which present the need to enhance the currently-applied solution. One method of processing higher order Delta Sigma bit-streams is the digital Delta Sigma modulator proposed. Based on the digital Delta Sigma modulator method and the proposed P-N (positive-negative) pair method with a signed binary counter, we design the Delta Sigma sum adder, average adder and coefficient multiplier. This paper is organized as follows: Section 2 presents the properties of a first-order Delta Sigma modulated bit-stream and the basic processing techniques using the proposed P-N pair method.
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