Hardware virtualization for protection against power analysis attack

Abstract

Field programmable gate arrays (FPGAs) are being increasingly used in diverse Internet of Things (IoT) application space. Poor programmability of FPGAs compared to their processor counterparts remains an important challenge amidst their wide-spread usage. On the other hand, security of FPGA-based systems against physical attacks, in particular, side-channel attacks (SCAs) has emerged as a critical concern. Hardware virtualization, where instead of directly mapping a design to FPGA, it is mapped on top of a generic architecture, called overlay, has been shown to address the programmability challenge, leading to significantly higher productivity and several orders of magnitude reductions in compile time as well as bitstream size. However, unlike software or network virtualization, FPGA virtualization has not been studied with respect to its security benefits. In this paper, for the first time to our knowledge, we propose to utilize the properties of virtualization to address the FPGA security issues against a dominant mode of SCA, namely, power analysis attack. We note that while virtualization shows many intrinsic security benefits, we can efficiently implement masking approaches in novel ways onto this architecture to achieve high level of protection. Extensive security analysis is done to show large side-channel resistance improvement for a set of evaluation metrics.