Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal

Abstract

To counteract logic-testing methods and trust verification methods for hardware Trojan (HT) detection, two HT design strategies based on high-low probability and partitioned combinational logic with a malicious reset signal are proposed. Using these two strategies, a power consumption HT and a forced reset HT are designed in a self-developed RISC-V processor. The processor is implemented using SMIC 55nm CMOS technology. Experiments show that, compared to the HTs designed with low-probability nets, the HTs designed with high-low probability strategy can reduce the triggering probability by 87.5%. The HT designed by partitioning combinational logic strategy can increase the false positive rate of HT to 40%. The result can defeat FANCI effectively. In order to enhance the stealth of the HTs, we partitioned combinational logic by using flip-flops with a malicious reset signal. The reset signal participates as a part of the trigger condition, which significantly reduces the trigger probability of HTs.