Hardware Transactional Memory in Multicore Processors

Abstract

The transactional memory in multicore processors has been a major area of research over past ten years. Many transactional memory architectures have been proposed to solve the synchronization problem of multicore processors. Hardware transactional memory is one of the critical methods to speedup communications between many cores. We give a review of the current hardware transactional memory systems for multicore processors. Hardware transactional memory systems are classified into the following two categories: whether to support unbounded transactional memory and whether to support transactions nesting. Finally, we discuss two active research challenges: the relationship between transactional memory and input/output operations and instruction set architecture supporting.