Abstract

The hardware-software synthesis of an embedded system's architecture involves the partitioning of a system specification into hardware and software modules so as to meet various non-functional requirements. A designer can specify many non-functional requirements including cost, performance, reliability etc. In this thesis, we present an approach to the hardware-software co-synthesis of embedded systems targeting hypercube topologies. Hypercube topologies provide a flexible and reliable architecture for an embedded device with multiple processing elements. To the best of our knowledge, this is the first time that hypercube topologies have been supported in a co-synthesis algorithm. The co-synthesis approach represented here supports the following features: 1)input in the form of an acrylic periodic task graph with real-time constraints, 2) the pipelining of task graphs, 3) the use of a heterogeneous set of processing elements, 4) Support for fault tolerance through our newly developed group based fault tolerance technique. The co-synthesis algorithm has been applied to two case studies to demonstrate its efficacy.

Highlights

  • This thesis presents a new hardw are-softw are co-synthesis tool to aid in the design and developm ent o f high performance embedded devices

  • A partitioning algorithm that operates at a high level o f granularity uses only large blocks o f system functionality to be implemented on any given processing elem ent (PE)

  • In the group based fault tolerance algorithm, if an error is detected on a given cluster, the entire functionality o f that cluster is m oved to a spare processing elem ent and signaled to recom m ence execution

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Summary

O verview

T h e average C anadian equates the idea o f a com puter w ith a desktop or laptop. In actuality, the definition o f a com puter is m uch broader. Em bedded com puters already pem ieate our society and their grov/th is expected to continue indefinitely It is com m on know ledge that technological developm ents are prpducing increasingly efficient and com pact com puters. An engineer will tell the CAD tool w hat the desired device should be capable o f doing; the tool will analyze the given inform ation and recom m end a reliable and efficient design This can aid a product engineer in developing system s that are far m ore reliable, cost, tim e and pow er efficient. M inim izing a dev ice’s pow er consum ption is essential to reducing energy costs, both financial and environm ental These CAD tools will aid in the developm ent o f new devices that will continue to play a central role in our lives. Developing these software tools can be technically challenging and intellectually rewarding

O riginal Contributions
T hesis O rganization
Introduction to H ardw are-Softw are Co-Design
H ardw are-Softw are Partitioning
Standard Approach
Partitioning Granularity
Dynamic Programming
H ardw are-Softw are Co-Synthesis
H ypercube Architectures
Introduction
Fault T olerance at the T ask G raph Level
Task Based Fault Tolerance
Cluster Based Fault Tolerance
Group Based Fault Tolerance
Task Graph Based Fault Tolerance Comparison
Pipelined Scheduler
Schedule
D evice Expansion
Com m unication Link Integration
Parallel M PEG -2 D ecoding
16 MPEG Decoders
Parallel Block M atching
Blockmalching and all Vector Assembly
CONCLUSIONS AND FUTURE WORK
Findings
E N T IT Y regS IS
H N D description

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