Hardware / Software Co-design using LEON3 Processor: AES as Case Study

Abstract

Nowadays many powerful public domain IP cores are available for complicated component like 32 bit processor i.e. LEON3. It needs considerable expertise and pain taking experimentation to implement a hardware/software co-design project. This paper presents step-by-step description for AES algorithm implementation on LEON3 processor. This will prove to be valuable to researchers working in this area and save their valuable time. The concept of GPIO (General Purpose I/O Port) is introduced; through which any custom hardware i.e. own designed hardware or IP core can be interfaced with the open source processor. AES encryption algorithm is selected as an IP core to be interfaced with LEON3 processor. AES is implemented in VHDL, while the control of the algorithm is in software. AES algorithm partitioned in hardware and software. The complete algorithm in hardware and control of algorithm in software. The part of algorithm in hardware is interfaced with the system designed using processor as a custom hardware and performance parameters studied. AES implemented using Codesign approach. AES is the latest encryption standard used to protect confidential information like financial data for government and commercial use. The LEON3 is a synthesizable VHDL model of a 32-bit processor available under the GNU GPL license. The design is implemented on Cyclone II FPGA from Altera Corporation.