Abstract
An algorithm proposed by Yingquan Zhou et al. (1995) for effectively reducing hardware overhead of the checking circuitry in the continuous checksums based concurrent error detection (CED) scheme in linear analog circuits is discussed. Without changing the original circuit, the algorithm generates such an appropriate coding matrix that makes the resulting checking circuitry have optimal hardware overhead.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
