Abstract

In the 21st century with the exponential growth of the Internet, the vulnerability of the network which connects us is on the rise at a very fast pace. Today organizations are spending millions of dollars to protect their sensitive data from different vulnerabilities that they face every day. In this paper, a new methodology towards implementing an Intrusion Detection & Prevention System (IDPS) based on Artificial Neural Network (ANN) onto Field Programmable Gate Array (FPGA) is proposed. This system not only detects different network attacks but also prevents them from being propagated. The parallel structure of an ANN makes it potentially fast for the computation of certain tasks. FPGA platforms are the optimum and best choice for the modern digital systems nowadays. The same feature makes ANN well suited for implementation in FPGA technology. Hardware realization of ANN to a large extent depends on the efficient implementation of a single neuron. However FPGA realization of ANNs with a large number of neurons is still a challenging task. The proposed multilayer ANN based IDPS uses multiple neurons for higher performance and greater accuracy. Simulation of the design in MATLAB SIMULINK 2010b by using Knowledge Discovery and Data Mining (KDD) CUP dataset shows a very good performance. Subsequently MATLAB HDL coder was used to generate VHDL code for the proposed design that produced Intellectual Property (IP) cores for Xilinx Targeted Design Platforms. For evaluation purposes the proposed design was synthesized, implemented and tested onto Xilinx Virtex-7 2000T FPGA device.

Highlights

  • Intrusion prevention is the process of performing intrusion detection and attempting to stop detected possible incidents

  • The proposed Intrusion Detection & Prevention Systems (IDPS) architecture consists of two blocks—an Intrusion Detection System (IDS), which classifies the attack and the Intrusion Prevention System (IPS), which takes the classified signature and decides which signatures to be propagated

  • The proposed IDPS architecture consists of two blocks—the Artificial neural networks (ANN) based Intrusion Detection System (IDS), which classifies the attack and the Intrusion Prevention System (IPS) designed using embedded MATLAB function, which takes the classified signature and decides which signatures to be propagated as indicated by the binary values of Intrusion Prevention (IP) status

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Summary

Introduction

Intrusion prevention is the process of performing intrusion detection and attempting to stop detected possible incidents. IDPS perform extensive logging of data that is related to detected events in the network. Real time applications are possible only if low cost high-speed neural computation is made realizable. Towards this goal numerous works on implementation of ANN have been proposed [2].

Proposed Architecture of ANN Based IDPS
Encoder
Feed Forward ANN
IDPS Implementation on FPGA
MATLAB Implementation of the Proposed IDPS Architecture
VHDL Modeling of the Proposed IDPS
FPGA Implementation of the Proposed ANN Based Architecture
Findings
Summary and Future Work
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