Abstract
A family of architecture-aware Raptor codes is constructed. The proposed construction scheme is targeted to design rate-compatible structured codes that span a wide range of rates and block sizes while still having hardware-efficient decoder implementations. The codes match the corresponding fixed-rate LDPC codes in error-correcting performance, decoding convergence speed, and message-memory requirements. Three novel steps are incorporated in the scheme: 1) a new group-based design of the code source matrix; 2) an architecture-aware row splitting-after-merging technique to construct irregular precodes; and 3) structured LT row-encoding. A code instance was designed accordingly and compared to standardized LDPC codes. The error-rate performance closely matches that of LDPC, whereas the convergence speed and message count gaps are narrowed down to values between [1.1x, 1.8x] and [1.1x, 1.3x], respectively.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
