Hardware optimized implementation of digital pulse compression based on FPGA

Abstract

for any radar system, the implementation of digital signal processing part based on FPGA is an important technology. This paper presents the FPGA based implementation of digital pulse compression algorithm for an LFM radar signal. Pulse compression is the expansion of frequency spectrum using matched filtering technique to improve the range resolution without affecting the long range detection performance of the radar system. For an LFM signal, fast convolution processing technique is used to implement the digital pulse compression algorithm using single FFT IP core both for FFT and IFFT operations. This algorithm reduces the number of complex multiplication in convolution and also reduces one FFT IP core to make the algorithm more optimized which is the focusing task of this article. Firstly, this algorithm is simulated in MATLAB and after that it is implemented on hardware using Xilinx FPGA and Xilinx ISE Design tool. Chosen FPGA is Virtex-5 (XUPV5-LX110T). For hardware implementation pipeline optimization is adopted during the implementation.