Hardware in the Loop Real-Time Simulation for the Associated Discrete Circuit Modeling Optimization Method of Power Converters

Xizheng Guo,Yiguo Tang,Xiaojie You,Jiaqi Yuan

doi:10.3390/en11113237

Xizheng Guo, Yiguo Tang + Show 2 more

Open Access

https://doi.org/10.3390/en11113237

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Journal: Energies	Publication Date: Nov 21, 2018
Citations: 8	License type: CC BY 4.0

Affiliation: Beijing Jiaotong University

Abstract

Due to the complicated circuit topology and high switching frequency, field-programmable gate arrays (FPGA) can stand up to the challenges for the hardware in the loop (HIL) real-time simulation of power electronics converters. The Associated Discrete Circuit (ADC) modeling method, which has a fixed admittance matrix, greatly reduces the computation cost for FPGA. However, the oscillations introduced by the switch-equivalent model reduces the simulation accuracy. In this paper, firstly, a novel algorithm is proposed to determine the optimal discrete-time switch admittance parameter, Gs, which is obtained by minimizing the switching loss. Secondly, the FPGA resource optimization method, in which the simulation time step, bit-length, and model precision are taken into consideration, is presented when the power electronics converter is implemented in FPGA. Finally, the above method is validated on the topology of a three-phase inverter with LC filters. The HIL simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the ADC modeling method, respectively.

Highlights

Hardware in the loop (HIL) real-time simulation of power electronics converters on field-programmable gate arrays (FPGA) has gained more attractiveness because it can meet challenges [1,2,3] relating to the more complex topology of power electronics converters and achieve a higher switching frequency, etc. [4,5,6,7,8]
The hardware in the loop (HIL) simulation and practicality experiments verify the effect of FPGA resource optimization and the validity of the Associated Discrete Circuit (ADC) modeling method, respectively
We can see the simulation waveform’s comparison of ADC modeling and PSB modules of three-phase inverter, and the relative errors are less than 1%

Summary

Introduction

Hardware in the loop (HIL) real-time simulation of power electronics converters on field-programmable gate arrays (FPGA) has gained more attractiveness because it can meet challenges [1,2,3] relating to the more complex topology of power electronics converters and achieve a higher switching frequency, etc. [4,5,6,7,8]. The modeling method of power electronics converters is a challenging task due to the changing topology of the circuit [9,10,11]. Modified nodal analysis (MNA) and the state-space approach require elaborate identification of all possible circuit states of power electronics converters, which can hardly be realized in real-time simulation [12,13,14]. The associate discrete circuit (ADC) modeling method presented by Pejovic [16,17], has a fixed admittance matrix by selecting the appropriate switch admittance parameter, Gs, which increases the simulation efficiency. A damping resistance can be added in series to the discrete-time switch model [18] This approach increases the model complexity as well as poses the problem regarding the optimum selection of the value of the damping resistance

Methods

Findings

Discussion

Conclusion