Abstract
Software Defined Radio (SDR) is widely used in wireless communication where Variable Digital Filter (VDF) plays a major role in extracting signals. The VDF allows the low pass, high pass, band pass and band stop frequency responses as per the given filter coefficients. In this paper, we implemented a variable digital filter (VDF) based on decimation using Constant Coefficient Multiplier (CCM). The proposed method is synthesized using Verilog in Xilinx Vivado software and implemented on Zynq-7020(XC7Z020-1CLG484) development board. The performance parameters are compared with previous implemented architectures in terms of area, power and latency. By the analysis it is clear that the proposed method is less complex and utilizes less area. The maximum operated frequency for the proposed VDF is 132.22 MHz.
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