Hardware implementation of SVM using system generator

Abstract

This paper presents an architecture based on FPGA for Support Vector Machine (SVM) classifier. SVM's training stage is done offline, and for further implementation of testing stage of SVM on hardware, the extracted parameters are being used. JAFFE (Japanese Association of Female Facial Expression) database which has three different emotional features is used for training and testing stage of SVM and the architecture is simulated using System Generator. The main characteristics of this research are simplicity in blocks and functions used to design the architecture and there is not any restriction on the sample numbers. Results obtained after synthesis for linear classification are nice with the accuracy of 97.87% and 132.626 Mega Hertz frequency.