Hardware implementation of subsampled adaptive subband digital predistortion algorithm

Abstract

Power amplifiers are key elements for transmission systems that have a high impact on transmission quality and energy consumption. While linearity constraints are set to minimize channel interference, power amplifiers are renowned to have a poor energy efficiency in their linear operation region. And reducing the energy footprint of communication systems is a main challenge for future telecommunication networks. Digital predistortion (DPD) is a technique that aims at linearizing power amplifiers and thus allows energy efficiency improvements. However, this technique usually requires to digitize the distorted signal over its entire bandwidth. Up to now, the distorted signals could be digitized using high-performance analog-to-digital converters (ADC). But, the expected increase in bandwidth for new standards will require even wider bandwidths for the DPD feedback path and larger computational resources. The power consumption caused by the additional parts for the DPD may limit the overall efficiency gain of the linearized system particularly for small-cells base stations. Recently, subband approaches have been proposed to relax the design constraints of the feedback path ADC and the digital processing unit in order to minimize the energy consumption of the DPD. We present in this paper a hardware implementation of a subsampled adaptive subband digital predistortion. We show that running the DPD algorithm on circuits synthesized for lower rate reduces the power consumption by a factor 26.9. This power consumption ratio is approximately five times larger than the subsampling ratio showing the interest of subsampled processing since low rate circuits are more power efficient than their high rate counterparts.